Programmable logic devices (PLDS) are integrated circuit devices with configurable logic networks linked together by programmable interconnection resources. The configurable logic networks may include device elements such as logic cells (e.g., look-up tables (LUTs) or product term logic), memory cells, and input-output cells. Registers (e.g., D-type flip-flops) may be associated with one or more of the device elements. The registers hold and transfer data signals (i.e., variables) between the device elements during device operation.
The device elements of a conventional PLD are often architecturally organized into blocks of programmable logic (e.g., gate array or logic array block (“LAB”)), blocks of input-output cells, and blocks of memory (e.g., random access memory (“RAM”)), etc. Groups of these blocks may make up larger blocks (i.e., “super-regions”) that are arranged, for example, in an X-Y array. The programmable interconnection resources of the PLD are organized as rows and columns of conductors for selectively routing signals to, from, and between the logic, input-output, and memory blocks. See, for example, Cliff et al. U.S. Pat. No. 5,550,782, Cliff et al. U.S. Pat. No. 5,689,195, and Jefferson et al. U.S. Pat. No. 6,215,326, all of which show PLD architectures developed by Altera Corporation of San Jose, Calif.; but other examples of architectures with which the present invention can be used include those developed by other PLD manufacturers such as Xilinx, Inc., also of San Jose, Calif.
Complex logic functions (circuits), as desired, may be implemented in present-day PLDs. The logic functions are implemented by interconnecting a select configuration of device elements according to a suitable circuit design. Conventional circuit design techniques for synthesis of logic functions may be used to generate a suitable circuit design. The circuit design may be characterized by a corresponding configuration file (i.e., a netlist) that specifies the placement and interconnection of selected device elements. PLDs usually have a large number of device elements that have identical functionality (e.g., AND gates) and which may be used interchangeably. Therefore, several possible circuit designs (i.e., configurations of device elements) may yield the same desired logic function.
The circuit design which is implemented is,:
usually, optimized for circuit performance. A measure of circuit performance is data signal propagation delay. This delay depends, inter alia, on the length of interconnection and on the number of registers between device elements traversed by data signals. A figure of merit of circuit delay performance is the length (in units of time) of the longest register-to-register delay path (“the critical path”) in the circuit. This critical path also determines the minimum cycle time for a logic step in the PLD device. The reference or master clock signal timing various device elements in the PLD is set to have a period or cycle which is greater than the minimum cycle time.
The PLD critical path length may be minimized using “re-timing” techniques for optimizing circuit designs. These techniques address the problem of optimal placement and interconnection of device elements by repositioning registers along the path of data signals. Registers associated with logic cells are repositioned from the cells, output to input or vice versa, so that the critical path is as short as possible. Some circuit designs must use device elements in different regions. For these designs, repositioning of registers along the data path between the device elements in different regions cannot reduce critical path length below the length of a long interconnection that must be used. For example, a PLD cross-chip critical path of about 25 ns may include a long interconnection along which the delay is about 8 ns. Then, the length of the longest interconnection 8 ns sets the smallest time unit or granularity for retiming operations.
Co-owned Hutton U.S. Pat. No. 6,429,681 shows, for example, a way of circumventing the lower bound on time delay due to the longest interconnection length in the data path. The disclosure therein describes the optional insertion of re-timing registers in the interconnections. An inserted retiming register effectively fragments the end-to-end interconnection time delay into two smaller time delay units.
Irrespective of the circuit design optimization techniques available or used, most of the chip area in commercially available PLDS is devoted to programmable interconnection resources. These interconnection resources are responsible for most of the circuit delay. Consideration is now being given to ways of enhancing programming logic device architectures to minimize the chip area devoted to interconnection resources or to reduce the interconnection conductor line count in a PLD.